SAW Fails To Import TabbyCAD JSON: Troubleshooting

by Alex Johnson 51 views

Introduction

This article addresses an issue encountered when using SAW (SAW-Script) to analyze hardware circuits. Specifically, SAW is unable to import JSON files generated by TabbyCAD, a commercial version of Yosys, even though it can import JSON files produced by Yosys itself. This problem arises during the VHDL verification process, as detailed in the VHDL verification tutorial. Let's dive into the specifics, potential causes, and possible solutions to resolve this incompatibility.

Background and Problem Description

When following the VHDL verification tutorial, the combination of yosys and ghdl allows for the successful loading of the resulting adder_yosys.json file into SAW. This process involves using Yosys to synthesize the VHDL code and generate a JSON representation of the circuit, which SAW then uses for verification.

However, when using TabbyCAD, which is a commercial alternative to Yosys, the process breaks down. The following commands are executed in TabbyCAD to generate the adder_tabby.json file:

yosys> read -vhd adder.vhdl
yosys> hierarchy -check -top add4
yosys> write_json adder_tabby.json

Despite the successful generation of the JSON file, attempting to import adder_tabby.json into SAW results in the following error message:

Error: Encountered a cell "$verific$i5$adder.vhd:15$37" with type "$_BUF_", but could not find a submodule named "$_BUF_".

This error suggests that the $_BUF_ cell, which seems to be inserted by Verific (the parsing engine used by TabbyCAD), is not recognized by SAW. The issue raises two key questions:

  1. Is there a specific setting or command-line option that needs to be used with TabbyCAD to produce SAW-digestible output? If so, the tutorial should be updated to reflect this. This would ensure that users of TabbyCAD can seamlessly integrate their designs with SAW.
  2. If no specific setting exists, should SAW be updated to handle VHDL designs parsed by Verific, given that TabbyCAD is a commercial version of Yosys?

Analyzing the Root Cause

The error message indicates that SAW is unable to find a submodule named $_BUF_. This suggests a discrepancy in how Yosys and Verific handle basic buffer cells. While Yosys might represent buffers in a way that SAW understands, Verific's representation seems to be incompatible.

It's important to understand the role of Verific in this process. Verific is a VHDL parsing and elaboration tool used by TabbyCAD. It reads the VHDL code and transforms it into an internal representation that Yosys can then synthesize. The $_BUF_ cell is likely an artifact of this parsing process.

The attached files, adder_yosys.json and adder_tabby.json, provide valuable insights. By comparing these files, we can identify the differences in how Yosys and TabbyCAD represent the same circuit. This comparison can help pinpoint the exact cause of the incompatibility.

Potential Solutions and Workarounds

Several potential solutions and workarounds can be explored to address this issue:

1. TabbyCAD Configuration

  • Investigate TabbyCAD Settings: The first step is to thoroughly investigate TabbyCAD's settings and command-line options. There might be a specific setting that controls how Verific generates the output netlist. Look for options related to compatibility with Yosys or other synthesis tools. It is possible that there is a setting that will allow TabbyCAD to produce output that is compatible with SAW.
  • Consult TabbyCAD Documentation: Refer to the TabbyCAD documentation for information on generating netlists for different synthesis tools. The documentation might provide specific instructions or recommendations for using TabbyCAD with SAW. The documentation is likely to contain details about how to configure TabbyCAD to output netlists in a format that is compatible with SAW.
  • Contact TabbyCAD Support: If the documentation doesn't provide a solution, consider contacting TabbyCAD support for assistance. They might be able to provide guidance on configuring TabbyCAD to work with SAW, or they might be aware of a known issue and have a workaround.

2. SAW Modification

  • Update SAW to Recognize Verific Cells: If TabbyCAD cannot be configured to produce SAW-compatible output, the alternative is to modify SAW to recognize the Verific-specific cells, such as $_BUF_. This would involve updating SAW's netlist parser to handle these cells correctly. This would make SAW more versatile and able to handle a wider range of netlist formats.
  • Provide a Translation Layer: Another approach is to create a translation layer that converts the TabbyCAD-generated JSON into a format that SAW can understand. This could be a script that reads the adder_tabby.json file and transforms it into a adder_yosys.json equivalent. This would allow users to continue using TabbyCAD without having to modify SAW directly. A translation layer would act as an intermediary, bridging the gap between the two tools.

3. Intermediate Synthesis Tool

  • Use Yosys as an Intermediate Step: One potential workaround is to use Yosys as an intermediate synthesis tool. This would involve using TabbyCAD to parse the VHDL code and then using Yosys to synthesize the resulting netlist. This approach would leverage TabbyCAD's parsing capabilities while ensuring that the final netlist is in a format that SAW can understand. This method would bypass the incompatibility issue by using Yosys to generate the final netlist.

Detailed Steps to Troubleshoot

To effectively troubleshoot this issue, follow these detailed steps:

  1. Examine the JSON Files: Conduct a thorough examination of both adder_yosys.json and adder_tabby.json. Use a text editor or JSON viewer to compare the structure and content of the files. Pay close attention to how cells, modules, and connections are represented in each file. Look for differences in the naming conventions, attribute values, and overall organization of the netlists.
  2. Identify the $_BUF_ Cell: Locate the $_BUF_ cell in the adder_tabby.json file. Analyze its attributes and connections to understand how it is being used in the circuit. Compare this to how buffers are represented in the adder_yosys.json file. This will help determine why SAW is unable to recognize the $_BUF_ cell.
  3. Consult Verific Documentation: Refer to the Verific documentation for information on the $_BUF_ cell and other Verific-specific constructs. The documentation might provide insights into the purpose of these cells and how they are intended to be used. It might also explain how to configure Verific to generate different types of netlists.
  4. Experiment with TabbyCAD Settings: Experiment with different TabbyCAD settings to see if any of them affect the generation of the $_BUF_ cell. Try disabling certain optimizations or using different synthesis options. Check if these changes make the output compatible with SAW. This process might involve trial and error to find the right combination of settings.
  5. Test with a Simpler Circuit: Create a simpler VHDL circuit that also uses buffers and try to synthesize it using both Yosys and TabbyCAD. This will help isolate the issue and determine if it is specific to the adder circuit or a more general problem. A simpler circuit will be easier to analyze and debug.

Conclusion

In conclusion, the incompatibility between SAW and TabbyCAD-generated JSON files stems from differences in how the two tools represent basic circuit elements, specifically the $_BUF_ cell. Resolving this issue requires a multi-faceted approach, including investigating TabbyCAD settings, potentially modifying SAW to recognize Verific-specific cells, or using an intermediate synthesis tool. By following the troubleshooting steps outlined in this article, users can work towards a solution that allows them to seamlessly integrate TabbyCAD designs with SAW for verification purposes.

For more information on hardware verification and related topics, you can visit the Formal Verification Wikipedia page.